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AR# 44111

AXI Bridge for PCI Express - How to adjust the transceiver settings


The AXI Bridge for PCI Express currently does not allow the transceiver settings such as pre-emphasis, differential swing, and equalization to be modified. Under certain conditions these settings, and possibly others, must be manually changed to establish a reliable link.


To access the transceiver ports, follow the instructions below:
  1. Create a local pcore by right-clicking the IP and selecting to bring it local.
  2. Within the new local pcore directory, navigate to the "/pcore/axi_enhanced_pcie_v2_00_a/hdl/verilog" directory.
    • For Spartan-6 FPGA, the transceiver wrapper is called gtpa1_dual_wrapper_tile.v.
    • For Virtex-6 FPGA, the transceiver wrapper is called gtx_wrapper_v6.v module.
    • For 7-Series, the transceiver wrapper is called pcie_7x_v1_#_gt_wrapper.v

After following these instructions, make sure to save the changes and clean your previously generated netlist within the EDK project.

Revision History:
04/11/2012 - Updated for 7 series
11/06/2011 - Initial Release
AR# 44111
Date Created 11/30/2011
Last Updated 04/11/2012
Status Active
Type General Article
  • ISE Design Suite - 13.2
  • AXI PCI Express (PCIe)