This issue occurs because the initialization block used in the Virtex-6 GTH IBERT core overrides the RXRATE, TXRATE, and SAMPLERATE.What this means is that these ports cannot be overwritten by the user at run time.
This issue will be fixed in the Virtex-6 GTH IBERT core in the 13.3 release of the ISE tools. This issue only affects the Virtex-6 GTH IBERT core and does not affect the Virtex-6 GTX IBERT core.
To workaround this issue, you will need to generate a separate IBERT design targeting the different line rates that you need to test your transceivers at. For example, if you want to run your transceiver at 11.18G and 5.59G, you generate an IBERT core for 11.18G and another IBERT core for 5.59G so that you have two separate bit files.