^

AR# 44140 13.2:XST - "WARNING:Xst:1710 - This FF/Latch will be trimmed during the optimization process..."


XST issues a warning similar to the following and trims the complete logic by connecting the out signal to ground:
"WARNING:Xst:1710 - FF/Latch <sreg_1> (without init value) has a constant value of 0 in block <bug_demo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <sreg_0> of sequential type is unconnected in block <bug_demo>.
WARNING:Xst:2677 - Node <sreg_0> of sequential type is unconnected in block <bug_demo>."

Is this trimming valid? If it is not, how do I fix it?

A sample code that showed this problem is as follows:

entity bug_demo is
Port ( Ext_In : in STD_LOGIC;
Ext_Out : out STD_LOGIC;
clk : in STD_LOGIC);
end bug_demo;
architecture Behavioral of bug_demo is
signal sreg : std_logic_vector(0 to 1);
signal reg_dx : std_logic_vector(0 to 1);
begin
Ext_Out <= reg_dx(1);
reg_dx <= sreg;
process(clk)
begin
if clk'event and clk = '1' then
sreg <= Ext_In & sreg(0);
end if;
end process;
end Behavioral;


In this particular case, XST should not have trimmed the internal signals and connected the output to GND. This is definitely an issue with XST and a CR has been filed to fix this problem.

Work-around:

Adding the KEEP attribute on the internal signal reg_dx fixes this logic trimming.

The same sample code with the work-around is as follows:
entity bug_demo is
Port ( Ext_In : in STD_LOGIC;
Ext_Out : out STD_LOGIC;
clk : in STD_LOGIC);
end bug_demo;
architecture Behavioral of bug_demo is
attribute KEEP : string;
signal sreg : std_logic_vector(0 to 1);
signal reg_dx : std_logic_vector(0 to 1);
attribute KEEP of reg_dx :signal is "TRUE";
begin
Ext_Out <= reg_dx(1);
reg_dx <= sreg;
process(clk)
begin
if clk'event and clk = '1' then
sreg <= Ext_In & sreg(0);
end if;
end process;
end Behavioral;
AR# 44140
Date Created 10/12/2011
Last Updated 10/12/2011
Status Active
Type
Devices
  • Spartan-6 LX
Tools
  • ISE Design Suite - 13.2
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