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AR# 44151

System Generator for DSP v13.x - What is the flow for bringing a design with a tri-state port through System Generator (black box) and finally into EDK?


What is the flow for bringing a design with a tri-state port through System Generator (black box) and finally into EDK?


In order to generate a custom pcore for EDK which contains a tri-state signal, use the following instructions:

1) In your HDL, rather than use a bidirectional data type, separately implement the three signals which will be used for the tri-state. Also, do not instantiate I/O buffers; EDK will infer the necessary buffers. Make sure to follow the coding style and naming conventions described on pages 68-69 of psf_rm.pdf (in the doc folder of the EDK install).

2) Bring your HDL into System Generator as a Black Box module and generate the pcore using the normal flow.

3) Copy the newly generated pcore into your EDK projects pcores folder.

4) Modify the MPD file to reflect the tri-state signals in your pcore, taking care to follow the same naming convention. Look at the top-level HDL generated by System Generator to ensure that all three signals were generated correctly according to psf_rm.pdf. Also, when modifying the MPD file, use the signal names as they appear in the top-level System Generator HDL. Use the tri-state signals in the GPIO core as a guide. The following is an example of the lines that must be added/modified in the MPD file.

As such, the MPD file was updated as follows:

 # Peripheral Options


 # Ports

PORT data_io = "", DIR=INOUT, VEC=[0:(8-1)], ENABLE=SINGLE, THREE_STATE=TRUE, TRI_I = data_I, TRI_O = data_O, TRI_T = data_T, PERMIT = BASE_USER, DESC = 'Data IO', IO_IF = data, IO_IS = data_io

PORT data_i = "", VEC = [0:(8-1)], DIR = IN, IO_IF = data, IO_IS = data_in

PORT data_o = "", VEC = [0:(8-1)], DIR = OUT, IO_IF = data, IO_IS = data_out

PORT data_t = "", DIR = OUT, IO_IF = data, IO_IS = tri_out

The top-level SysGen entity for this pcore was generated follows:

entity test_plbw is

port (

data_i: in std_logic_vector(0 to 7);

data_o: out std_logic_vector(0 to 7);

data_t: out std_logic;


end test_plbw;

From here, XPS should correctly recognize your tri-state ports and react appropriately.

For a more general description regarding MPD file configuration, refer to Chapter 3 of psf_rm.pdf

For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
29595 Xilinx DSP Tools, System Generator for DSP, and AccelDSP Synthesis Tool - Release Notes and Known Issues N/A N/A
AR# 44151
Date Created 08/03/2012
Last Updated 06/24/2013
Status Active
Type General Article
  • EDK - 13.2
  • System Generator for DSP - 13.2
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