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AR# 44173

Xilinx Memory Interface Solution Center - Design Assistant

Description

Select the appropriate Design Assistant below to learn more about designing with a MIG core or to find help on debugging an issue that you are currently encountering.

The MIG Design Assistants walk you through the recommend design flow for MIG while debugging commonly encountered issues such as simulation issues, calibration failures, and data errors.

The Design Assistants provide useful design and troubleshooting information, but also point you to the exact documentation you need to read to help you design efficiently with MIG.

Note: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243).

The Xilinx MIG Solution Center is available to address all questions related to MIG. 

Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

UltraScale Memory

MIG IP UltraScale Design Checklist
  • Starting with UltraScale Memory, all design and debug content is organized based on the recommended design flow for MIG within the MIG IP UltraScale Design Checklist.
    Please use this checklist through your MIG IP design and debug.
7 Series Memory

(Xilinx Answer 51313) MIG 7 Series Design Assistant
Virtex-6 Memory

(Xilinx Answer 34266) MIG Virtex-6 Design Assistant
Spartan-6 Memory

(Xilinx Answer 37496) MIG Spartan-6 Design Assistant

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34243 Xilinx Memory Interface Solution Center N/A N/A

Child Answer Records

AR# 44173
Date Created 09/19/2011
Last Updated 11/11/2016
Status Active
Type Solution Center
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Spartan-6 LX
  • Spartan-6 LXT
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Less
IP
  • MIG Virtex-6 and Spartan-6
  • MIG 7 Series