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AR# 44192

Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices


Lower Power Spartan-6 FPGA -1L speed files do not match the data sheet values for block RAM fMAX. This issue to be fixed in ISE Design Suite 13.3 and later.Thepatch belowcan be installed to run timing analysis for earlier software versions.


10/26/2011 Update

The original patches provided with the README (dated 9/22/2011) did not include the speed files for theautomotive (XA) or military (XQ) devices. All of the patches listed below are now updated and include these devices. You can confirm theupdated patch by the README dated 10/26/2011. Since the issue listed in this answer record only affects the -1L speed grade parts, which are not available in XA or XQ, this change does not affect the block RAM fMAX issue. However, the issue in (Xilinx Answer 44193) is affected, so the speed file patch was updated.


Lower Power Spartan-6 FPGA -1L speed files are scheduled to be updated in ISE Design Suite 13.3 to correct errors in the block RAM fMAX.The correct value has always been shown in the production specifications in the data sheet; this update makes the speed files match the data sheet. Designs that might be affected by the change(detailed below) should be evaluated to confirm that they meet timing.Timing analysis can be run in ISE 13.3 software when it is available, or a speed file patch can be applied to run analysis on an earlier software version. To receive the patch, see the Work-around section below.

The ISE 13.2 software speed file version is v1.07 for the lower power Spartan-6 -1L devices.The corrected speed file is v1.08.

In addition to the -1L speed files, all other Spartan-6 FPGA speed files are being updated in ISE 13.3 softwarefor the DCM Phase Alignment values (Xilinx Answer 44193).

Block RAM fMAX Change for -2 and -1L Speed Grades

The block RAM maximum frequency is being reduced from 250 MHz to 150 MHz for the -1L speed grade, for Lower Power Spartan-6 -1L devices running at a reduced VCCINT.The -1L speed file went to production status in ISE 13.1 and 13.2, and this affects both the general purpose devices and the Spartan-6Q devices. The new value will match the values shown in the Spartan-6 Data Sheet (DS162); seeTable 43, fMAX.

In addition, the -2 speed grade fMAX is being improved in the Spartan-6 Data Sheet (DS162) from 260 MHz to 280 MHz to match the current speed file value of 280 MHz. The 280 MHz value will apply to all past, present, and future Spartan-6 production devices in the -2 and -2Q speed grade.


Thefollowing tablesummarizes the changes being made in the Spartan-6 FPGAspeed files with respect to the block RAM fMAX.

Block RAM fMAX
-3, -3Q
-3N -2, -2Q
ISE 13.1 and 13.2 320 MHz 280 MHz 280 MHz
250 MHz
ISE 13.3
320 MHz

(no change)

280 MHz

(no change)

280 MHz

(increased in data sheet

from 260 MHz)

150 MHz

(reduced in speed file)


Verify designs to confirm that they meet these timing requirements. To use the updated values in timing analysis, either use ISE 13.3 or later software when it is available, or install the patch below for the specific software version needed. Please note thatthe patches below are the same as listed in (Xilinx Answer 44193), so one installation covers both items. Review the included README.txt for install instructions.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46792 Spartan-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems N/A N/A
34856 Design Advisory Master Answer Record for Spartan-6 FPGA N/A N/A
AR# 44192
Date Created 09/22/2011
Last Updated 05/19/2012
Status Active
Type Design Advisory
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 12.4