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AR# 44208

Performance degradation of Xilinx Transceivers when using System Verilog with Synplify F-2011.09


Customers who are using the synthesis tool Synplify (version F-2011.09) from Synopsys with System Verilog might see a performance degradation on the Xilinx Transceivers in their design. This answer record explains the issue and the work-around.



When System Verilog is used with the synthesis tool Synplify (F-2011.09) from Synopsys, the tool inserts a BUFG after the IBUFDS_GTXE1. This causes the ISE tools to connect the output of a BUFG to the GREFCLK port of the transceiver as a reference clock instead of the dedicated reference clock ports. This issue has been observed on Virtex-6 FPGA GTX designs, but could also impact transceivers of other Xilinx FPGAs.

GREFCLK has the lowest performance of all of the available clock inputs to the Virtex-6 FPGA transceivers. This is because FPGA clocking resources can introduce jitter for operation at high data rates. Therefore, this might cause performance degradation with the transceivers.


The work-around is to add the attribute "syn_noclockbuf = true" on every reference clock net coming out of the IBUFDS_GTXE1. This will ensure that a BUFG is not inserted automatically by Synplify and the proper transceiver reference clock will be selected (resulting in no fabric dependent jitter).

Starting with ISE Design Suite 13.4, there is a DRC check that will output an error if the work-around is not used.
AR# 44208
Date 10/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • More
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • ??????
  • Less
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ??????
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