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AR# 44215 7 Series Integrated Wrapper for LogiCORE CPRI - v4.1- Should the transceiver transmit and receive elastic buffers be enabled?

Description

Should the transceiver transmit and receive elastic buffers should be enabled?For more information, please see(Xilinx Answer 43244).

Solution

To enable the transceiver transmit and receive elastic buffers:

  • Set RXBUF_EN to "TRUE" in the <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd file.
  • Set TXBUF_EN to "TRUE" in the <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd file.
  • In the same file, set RX_XCLK_SEL to "RXREC" .
  • In the same file, set TX_XCLK_SEL to "TXOUT".
  • In addition, disable the transmit and receive phase alignment.

Set the RX Elastic Buffer and Phase Alignment Ports section of <component_name>/example_design/gtx_and_clocks/gtx/v7_gtwizard_gt.vhd to:

-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------

RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXDDIEN => tied_to_ground_i,
RXDLYBYPASS => tied_to_vcc_i,
RXDLYEN => tied_to_ground_i,
RXDLYOVRDEN => tied_to_ground_i,
RXDLYSRESET => tied_to_ground_i,
RXDLYSRESETDONE => open,
RXPHALIGN => tied_to_ground_i,
RXPHALIGNDONE => open,
RXPHALIGNEN => tied_to_ground_i,
RXPHDLYPD => tied_to_ground_i,
RXPHDLYRESET => tied_to_ground_i,
RXPHMONITOR => open,
RXPHOVRDEN => tied_to_ground_i,
RXPHSLIPMONITOR => open,
RXSTATUS => open,

Set the TX Elastic Buffer and Phase Alignment Ports section of the same file to:

----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------

TXBUFSTATUS => open,
TXDLYBYPASS => tied_to_vcc_i,
TXDLYEN => tied_to_ground_i,
TXDLYHOLD => tied_to_ground_i,
TXDLYOVRDEN => tied_to_ground_i,
TXDLYSRESET => tied_to_ground_i,
TXDLYSRESETDONE => open,

For more information, see the LogiCORE CPRI Release Notes and Known Issues (Xilinx Answer 36969).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43244 Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon N/A N/A
44010 7 Series Integrated Wrapper for LogiCORE CPRI - GTXE2_COMMON Use Model Change N/A N/A
44011 7 Series Integrated Wrapper for LogiCORE CPRI - IBUFDS_GTE2 Use Model Change N/A N/A
44012 7 Series Integrated Wrapper for LogiCORE CPRI - TXOUTCLK and RXOUTCLK Port Restrictions N/A N/A
43339 7 Series FPGA GTX Transceiver - Software Use Model Changes N/A N/A

Actions

AR# 44215
Date Created 10/05/2011
Last Updated 08/28/2012
Status Active
Type Known Issues
IP
  • CPRI
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