UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44228

14.x Timing - The equation of Clock Uncertainty for PLL/DCM/MMCM

Description

What is the equation for the Clock Uncertainty for PLL/DM/MMCM?

Solution

Following is the equation for DCM Clock Uncertainty:

Clock Uncertainty = ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE

DCM Discrete Jitter and DCM Phase Error are provided in the speed files for Virtex-4 devices and newer. However, DCM Discrete Jitter and DCM Phase Error are not available in speedprint.

Examples:
INPUT_JITTER [TIJ]: 200ps = 40000ps
SYSTEM_JITTER [TSJ]: 150ps = 22500ps
DCM Discrete Jitter [DJ]: 120ps
DCM Phase Error [PE]: 0ps
Clock Uncertainty: 185ps

Following is the equation for PLL/MMCM Clock Uncertainty:

Clock Uncertainty = ((DJ^2 + TIJ^2)^1/2) / 2 + PE

AR# 44228
Date Created 04/30/2012
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • More
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less