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AR# 44351

7 Series Intetgrated Block for PCI Express - Blocks on Left Side Might Exhibit Unpredicatable Behavior when using ISE Design Suite 13.2


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

When usingtheleft hand side or the "X0" locationintegrated blocks for PCI Express in Virtex-7 FPGA, it is possible to get unpredictable behavior, includinga failure to perform receiver detect,due to an issue with implementation software incorrectly assigning attributes to the block.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


There is no workaround for this issue. If you experience any odd behavior when using left hand side blocks, it is recommended to try and use the blocks directly acrossthe device (right hand side or the "X1" blocks) until ISE Design Suite13.3 is available. This issue is fixed in ISE Design Suite 13.3. However, if this is not possible, please open a WebCase with Xilinx Technical Support and refer to this answer record number.

Revision History
12/06/2011 - Added version resolved reference to AR 40469
10/06/2011 - Initial Release
AR# 44351
Date Created 10/06/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
  • Virtex-7
  • ISE Design Suite - 13.2