^
Advanced Search

AR# 44352 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Incorrect Pinout Generated in the "Verify Pin Changes and Update Design" Flow

Description

In MIG 7 Series v1.3, an incorrect pinout can be generated when using the "Verify Pin Changes and Update Design" flow with a PRJ file that was originally created using the "Fixed Pin Out" mode and with using a UCF with a pinout that has been modified. This issue only exists if the PRJ file passed to MIG was generated using the "Fixed Pin Out" mode and not if generated with "New Design - banks selection" mode.

Solution

When you generate a design in the "Fixed Pin Out" mode, the PRJ file stores the pin information. When the PRJ and UCF files are passed to the "Verify Pin Changes and Update Design" flow, instead of loading the new pinout from the UCF file, the original pin out is loaded from the PRJ file. Therefore, the generated pinout will be different from expected.

Workaround:

After passing UCF and PRJ files and clicking on the Next button, use the "ReadUCF" option and load the pinout from the UCF to override the PRJ pinout.

This issue is scheduled to be fixed in the MIG 7 Series v1.4 ISE 13.4 Design Suite release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Actions

AR# 44352
Date Created 09/30/2011
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series
Feed Back