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AR# 44353

7 Series Integrated Block for PCI Express - How to Target the Kintex-7 Integrated Block Wrapper to the KC705 Boards

Description


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

How do I target the KC705 boards?

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution


After ISE Design Suite 13.3 is available, update to ISE 13.3 and the v1.2 core.

ISE Design Suite 13.3
During the customization process, there is an option on GUI panel 10 that allows the selection of the Xilinx Development Board being used. Currently, there are options for the KC705 REV A and REV B boards. If you have REV C, the pinout is the same as REV B so select the REV B option. No other changes are necessary when using ISE Design Suite 13.3.

ISE Design Suite 13.2
You must first download the v1.1 rev 2 core patch. See (Xilinx Answer 40469) to get this patch and other known issues. After ISE Design Suite 13.3 is released, you are encouraged to migrate to the v1.2 core.

The two versions of the KC705 board available are: the Rev B and Rev C board.

First target the xc7k325t-ffg900-2 in CORE Generator, which will produce a UCF file in the generated core's example_design directory. Two changes need to be made when using the v1.1 Rev 2 core to target the KC705 rev B and C boards.

UCF File Change

1. Add the location and IO Standard of the sys_rst_n pin:
NET "sys_rst_n" IOSTANDARD = LVCMOS18 | PULLUP | NODELAY | LOC = G25;

2. Change the location of the IBUFDS:
INST "refclk_ibuf" LOC = IBUFDS_GTE2_X0Y1;

Wrapper File Change

Modify the pipe_clock.v file found in the generated core's source directory and replace the instantiation of the BUFGCTRL with the following:

////---------- Select Reference Clock --------------------------------------------
//BUFGCTRL refclk_i
//(
// //---------- Input -------------------------------------
// .CE0 (1'd1),
// .CE1 (1'd1),
// .I0 (CLK_TXOUTCLK),
// .I1 (CLK_CLK),
// .IGNORE0 (1'd0),
// .IGNORE1 (1'd0),
// .S0 (!REFCLK_SEL),
// .S1 ( REFCLK_SEL),
// //---------- Output ------------------------------------
// .O (refclk)
//);

//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))

begin : refclk_i

//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(

//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)

);

end

else

begin : txoutclk_i

//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(

//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)

);

end

endgenerate

Revision History
12/06/2011 - Added version resolved reference to AR 40469
10/19/2011 - Updated for ISE Design Suite 13.3
10/6/2011 - Initial Release
AR# 44353
Date Created 10/06/2011
Last Updated 12/06/2011
Status Active
Type Known Issues
Devices
  • Kintex-7
IP
  • 7 Series Integrated Block for PCI Express ( PCIe )