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AR# 44356

MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Truncation issue in the system clock period calculation

Description

MIG 7 Series v1.3 truncates the system clock period which causes component switching limit errors and error messages on some of the memory timing parameters in simulations. This issue only appears for input clock frequencies above 350 MHz.

Solution

MIG 7 Series v1.3 asks the user to select a memory clock period that is derived from the chosen input clock frequency with the help of the Clocking Wizard. During this process, frequencies must be converted to periods (and vice versa) for MIG and the Clocking Wizard. In order to perform this conversion, a truncation mechanism is used for the system clock frequencies which results in a lower output period from PLL than the supported memory clock period. The out-of-range memory frequency then causes the component switching limit errors and simulation error messages.

Changing the input clock frequency to a value less than 350 MHz prevents this issue from occurring. This problem is scheduled to be fixed in the MIG 7 Series v1.4 (in ISE 13.4 software release).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
AR# 44356
Date Created 10/03/2011
Last Updated 05/26/2014
Status Archive
Type Known Issues
Devices
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series