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AR# 44405

LogiCORE IP JESD204 - Release Notes and Known Issues

Description

This answer record contains the Release Notes for the LogiCORE IP JESD204 core and includes the following:

  • New Features
  • Device Support
  • Resolved Issues
  • Known Issues
  • Release notes for previous versions of the core

Solution

LogiCORE IP JESD204 v3.2
 
NOTE: Not recommended for new designs

 

New Features

ISE Design Suite

  • Hierarchy updated - Clocking resources have moved from the Block Level to the Example Design
  • Increase rx_buffer_adjust from 256 to 1024
  • The core now supports 1, 2, 3, 4, 5, 6, 7, and 8 lane configurations in 7-Series Devices
  • 12.5 Gbps line rate (in compatible devices)
  • Removed JESD204A
  • Added three new test modes
  • Software lane select

Vivado Design Suite

  • JESD204 v3.2 is not supported in Vivado 

 

Device Support

ISE Design Suite

The following device families are supported by the core for this release.

  • Kintex-7
  • Zynq-7000 AP SoC (xc7z030 and xc7z045)

Vivado Design Suite

The following device families are supported by the core for this release.

  • None

 

Resolved Issues

  • Fix for rx_cfg_sysref_always not initialized in the block level for an Rx core.

 

Known Issues

 

 

 

LogiCORE IP JESD204 v3.1

New Features

ISE Design Suite

  • JESD204 V3.1 is not supported in ISE 14.4, the latest core version available in ISE is V2.2

Vivado Design Suite
  • 2012.4 tool support
  • The core now supports 1, 2, 3, 4, 5, 6, 7 and 8 lane configurations in 7 series devices
  • Added support for Zynq-7000 xc7z030 and xc7z045 devices
  • 12.5 Gb/s line rate
  • Removed JESD204A
  • Added three new test modes
  • Software lane select
  • Hardware demonstration design for KC705


Device Support

ISE Design Suite

The following device families are supported by the core for this release.

  • None

Vivado Design Suite

The following device families are supported by the core for this release.
Operation at line rates up to 10.3125 Gb/s supported in:

  • Kintex-7 (Production)
  • Virtex-7 (Pre-Production)

Resolved Issues
  • None

Known Issues
  • (Xilinx Answer 55857)-JESD204B - v4.0 or earlier - Updated RX Termination settings for 7-Series GTP and GTH


 

LogiCORE IP JESD204 v2.2


Update

ISE Design Suite

  • ISE 14.4 design tools support


Device Support

ISE Design Suite

The following device families are supported by the core for this release.

  • Operation at line rates up to 6.25 Gb/s supported in: Virtex-6

Resolved Issues

  • None

Known Issues

  • 8 Lanes not supported. An 8-lane core can be generated by the IP Customization GUI even though the maximum number of lanes supported in Virtex-6 devices is 4.
  • Core incorrectly marked superseded: The JESD204 V2.2 core can only be selected if "Show All IP Versions" is selected in core Generator and is marked superseded in Virtex-6 devices, which is not correct. JESD204 V2.2 is the latest version supporting Virtex-6 devices and should be marked production.
  • (Xilinx Answer 55857) -JESD204B - v4.0 or earlier - Updated RX Termination settings for 7 series GTP and GTH


New Features

ISE Design Suite

  • ISE 14.2 design tools support
  • Added support for Virtex-7 devices with GTH Transceivers

Vivado Design Suite

  • 2012.2 design tools support
  • Added support for Virtex-7 devices with GTH Transceivers

Device Support

ISE Design Suite

The following device families are supported by the core for this release.

  • Operation at line rates up to 6.25 Gb/s supported in:
    • Virtex-6
  • Operation at line rates up to 10.3125 Gb/s supported in:
    • Kintex-7 (Pre-Production)
    • Virtex-7 (Pre-Production)

Vivado Design Suite

The following device families are supported by the core for this release.

  • Operation at line rates up to 6.25 Gb/s supported in:
    • Virtex-6
  • Operation at line rates up to 10.3125 Gb/s supported in:
    • Kintex-7 (Pre-Production)
    • Virtex-7 (Pre-Production)

Resolved Issues

  • CR599942: Allow alignment characters to be received in single lane mode by using the LMFC buffer in subclass 0. Note that because of this GTX channel bonding is no longer used in subclass 0.

Known Issues

  • (Xilinx Answer 55857)-JESD204B - v4.0 or earlier - Updated RX Termination settings for 7-Series GTP and GTH

 

 

 

LogiCORE IP JESD204 v2.1

New Features

ISE Design Suite

  • ISE 14.1 design tools support
  • The core now supports 1, 2, 4 and 8 lane configurations in 7 series devices (JESD204B Only)
  • Added support for Transceiver sharing between Transmit and Receive in 7 series devices
  • Added support for Virtex-7 devices with GTX Transceivers

Vivado Design Suite

  • 2012.1 design tools support
  • The core now supports 1, 2, 4 and 8 lane configurations in 7 series devices (JESD204B Only)
  • Added support for Transceiver sharing between Transmit and Receive in 7 series devices
  • Added support for Virtex-7 devices with GTX Transceivers

Device Support

ISE Design Suite

The following device families are supported by the core for this release.

  • Operation at line rates up to 6.25 Gb/s supported in:
    • Virtex-6
  • Operation at line rates up to 10.3125 Gb/s supported in:
    • Kintex-7 (Pre-Production)
    • Virtex-7 (GTX Only) (Pre-Production)

Vivado Design Suite

The following device families are supported by the core for this release.

  • Operation at line rates up to 6.25 Gb/s supported in:
    • Virtex-6
  • Operation at line rates up to 10.3125 Gb/s supported in:
    • Kintex-7 (Pre-Production)
    • Virtex-7 (GTX Only) (Pre-Production)

Resolved Issues

  • None

Known Issues

 

 

LogiCORE IP JESD204 v1.1

New Features

  •  First Release
  •  ISE Design Suite 13.3 support
  • JESD204A specification support
  • JESD204B specification support (Pre-Production)

Device Support

  • Operation at line rates up to 6.25 Gb/s supported in:
    • Virtex-6
    • Kintex-7 (Pre-Production)

Resolved Issues

  • None

Known Issues

  • (Xilinx Answer 44946) -Why I do not see the example design files when the core is generated?
  • (Xilinx Answer 44637) -How can I change CPLLLOCKDETCLK in the example design to have a free running clock independent clock as an input?
  • (Xilinx Answer 44957) -Is it possible to use the IP core for different line rates and different reference clocks?
  • (Xilinx Answer 55857) -JESD204B - v4.0 or earlier - Updated RX Termination settings for 7-Series GTP and GTH

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 44405
Date Created 10/26/2011
Last Updated 10/14/2014
Status Active
Type Release Notes
IP
  • JESD204