(Xilinx Answer 43244) recommends that Tx and Rx elastic buffers be enabled.
For OBSAI, these buffers are normally bypassed to allow accurate latency measurement for Round Trip Time (RTT) measurement, etc. Enabling the elastic buffers results in inaccurate RTT measurements.
In <component_name>/example_design/gtx_and_clocks/gtx/gtx_wrapper_gt.vhd, modify the Rx and Tx Elastic Buffer sections as follows:
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
RXBUFRESET => tied_to_ground_i,
RXBUFSTATUS => open,
RXDDIEN => tied_to_ground_i,
RXDLYBYPASS => tied_to_vcc_i,
RXDLYEN => tied_to_ground_i,
RXDLYOVRDEN => tied_to_ground_i,
RXDLYSRESET => tied_to_ground_i,
RXDLYSRESETDONE => open,
RXPHALIGN => tied_to_ground_i,
RXPHALIGNDONE => open,
RXPHALIGNEN => tied_to_ground_i,
RXPHDLYPD => tied_to_ground_i,
RXPHDLYRESET => tied_to_ground_i,
RXPHMONITOR => open,
RXPHOVRDEN => tied_to_ground_i,
RXPHSLIPMONITOR => open,
RXSTATUS => open,
----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
TXBUFSTATUS => open,
TXDLYBYPASS => tied_to_vcc_i,
TXDLYEN => tied_to_ground_i,
TXDLYHOLD => tied_to_ground_i,
TXDLYOVRDEN => tied_to_ground_i,
TXDLYSRESET => tied_to_ground_i,
TXDLYSRESETDONE => open
For Release Notes and Known Issues for the LogiCORE IP OBSAI, see (Xilinx Answer 36971).
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 36971 | LogiCORE IP OBSAI - Release Notes and Known Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 43339 | 7 Series FPGA GTX Transceiver - Software Use Model Changes | N/A | N/A |
| 43244 | Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon | N/A | N/A |