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AR# 44421 Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage

Description

iMPACT 13.2 indirect SPI flash or BPI flash programming operations can fail on Kintex-7 devices when the following two conditions are met:

  • Kintex-7 FPGA is in a JTAG chain position other than the first device.
  • Kintex-7 FPGA CFGBVS pin = 2.5V or 3.3V.

When the scenario above is met, iMPACT 13.2 loads the incorrect Kintex-7 FPGA indirect flash programming core that configures the I/O in banks 0, 14, and 15 with the 1.8V LVCMOS standard, instead of the 2.5/3.3V-compatible LVCMOS standard.

In some cases,it might appear that thecore file has not loaded with the following messages in the console (the core in fact is loaded but, is reported as not loaded incorrectly):

"INFO:iMPACT - Downloading C:\Xilinx\13.3\ISE_DS\ISE\data\cse\cseflash\kintex7\xc7k325t_xsdbbpi_lvcmos18 .cor core file.
INFO:iMPACT - Creating XC7K325T device.
PROGRESS_START - Starting Operation.
'2': Programming device...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:Cse - Status register values:
INFO:Cse - 0011 1111 0101 1110 0000 1000 0100 0010
INFO:Cse - '2': Completed downloading bit file to device.
INFO:Cse - '2': Programming completed successfully.
PROGRESS_END - End Operation.
Elapsed time = 6 sec.
Core is not loaded."

How do I work around this issue and what is the risk for my device?

Solution

Risk

For the XC7K325T Initial ES devices, the incorrect core can cause potential I/O damage over an extended period.

Work-arounds

  1. Ensure that the Kintex-7 FPGA is the first device in the JTAG chain (devices after the Kintex-7 FPGA do not affect this).
  2. There is a patch available.
    1. Download the archive from thefollowing link:
      http://www.xilinx.com/txpatches/pub/swhelp/ise13_updates/44421.zip
    2. Browse to your Xilinx ISE Design Suite installation. For example, on Windows it would be C:\Xilinx\13.2.
    3. Extract the archive "44421.zip" fileinto this ISE Design Suite installation directory.
    4. Use "Add BPI flash" flow as normal; the core is detected and flash devices can be selected as per the normal flow.

Fix Schedule

The fix provided in the patch for this issue is to be included in the 13.3 ISE Design Suite release.

NOTE: This issue does not affect the KC705 development board asithas only the Kintex-7 device in the JTAG chain.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42946 Design Advisory Master Answer Record for Kintex-7 FPGA N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A
40905 7 Series - ISE 13.x Software Known Issues related to the 7 Series FPGAs N/A N/A
50079 Kintex-7 FPGA KC705 Evaluation Kit - Board Debug Checklist N/A N/A

Actions

AR# 44421
Date Created 10/11/2011
Last Updated 08/30/2012
Status Active
Type Design Advisory
Devices
  • Kintex-7
Tools
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
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