A port signal is registered for the purpose of ChipScope logic analyzer probing. However, because the registered net is loadless, XST removes this registered net by default. To prevent this registered net removal, a valid option is to attach an S attribute to this registered net. The sample code is as follows:
(*S="TRUE"*)reg cs_Enable;
always @(posedge Clock) begin
cs_Enable <= Enable;
end
However, XST does not honor this attribute and still removes the cs_Enable signal, which results in the following warning message:
"WARNING:HDLCompiler:1127 - "C:\case\2011.10\gold_code_ver_217\sub_a.v" Line 23: Assignment to cs_Enable ignored, since the identifier is never used"
The alternative option of using the KEEP attribute to this registered cs_Enable net does not make any difference, either. How can I keep this signal so that it appears in ChipScope Inserter?
This is an XST issue and the problem is only seen with the new XST parser and is specific to Verilog designs only. A CR has been filed.
If the same Verilog design is synthesized with V5 and older target devices, the attribute takes effect as expected. The VHDL designs do not have this problem.
A viable workaround to this problem is to define an extra dummy signal and assign the registered net with the attached KEEP or S attribute to this dummy signal. This allows the warning to be transferred to the dummy signal and the registered net is not removed. The example code is as follows:
wire dummy_Enable;
(*S="TRUE"*)reg cs_Enable;
always @(posedge Clock) begin
cs_Enable <= Enable;
end
assign dummy_Enable =cs_Enable;