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AR# 44476

LogiCORE IP 10-Gigabit Ethernet MAC v11.2 (AXI) - Release Notes and Known Issues for ISE Design Tools 13.3

Description

This answer record contains the Release Notes for the LogiCORE IP 10-Gigabit Ethernet MAC v11.2 core, which was released in ISE Design Suite13.3, and contains the following information:

  • New Features
  • Supported Devices
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator software known issues, and design tools requirements, see the IP Release Notes Guide(XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features:

  • ISE 13.3 software support

Supported Devices:

  • Virtex-7
  • Virtex-7 -2G
  • Virtex-7 XT*
  • Kintex-7
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Virtex-6 -1L XQ LXT/SXT
  • Spartan-6 XC LX/LXT, -3 and -4

*To access these devices in the ISE Design Suite, contact your Xilinx FAE.

Resolved Issues:

  • Functional simulation does not work on VCS (CR 576013)
    Description: VCS does not support the function call to calculate a localparam value used in the AXI4-Lite to IPIF bridge block. This function call has been reimplemented in a way that VCS will support.
  • AXI FIFO in example design can repeat the last word of data (CR617619)
    Description: If a frame has a full 64 bits valid in the final transfer of data for a frame, the data can be repeated and added as the first word in the next frame.
  • AXI TX FIFO in example design can get stuck FULL (CR605857)
    Description: The AXI FIFO waits for the end(tlast) of the frame to clear the FULL flag. If a flow control capable master is writing tready is de-asserted when full is asserted, then the master holds the data and tvalid and last is never asserted. This causes the TX FIFO to get stuck in FULL state forever.
  • In-band FCS and DIC cannot be enabled together on config vector (CR592405)
    Description: In-band FCS and DIC can be turned on at the same time when the AXI-Lite/IPIF interface is used, but when the configuration vector is used the Deficit Idle Count bit is inhibited.

Known Issues:

  • TX/RX MTU size is unconstrained (CR 608810).
    Description: Although only values of 1518 or greater are legal for TX and RX MTU size, the core will not enforce this size on write. Please ensure only legal values are written to the MTU register for correct core operation.
  • (Xilinx Answer 45081) LogiCORE IP 10-Gigabit Ethernet MAC v11.2 (AXI) - Core Returns Incorrect Version Number
AR# 44476
Date Created 10/11/2011
Last Updated 05/19/2012
Status Active
Type Release Notes
IP
  • 10 Gigabit Ethernet Media Access Controller