We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 44500

XST - Multiple dimension in gate instantiation in RTL code causes "ERROR:HDLCompiler:1821" beginning ISE 13.3 software


Starting from ISE 13.3, the XST new parser will give the following error when the XST new parser encounters a multidimensional instantiation label in an array of instances.

The XST new parser prior to version 13.3 did not give any error or warning for this.

The sample error message is as follows:

ERROR:HDLCompiler:1821 - "test_1821.v" Line 16: Multiple dimension in gate instantiation ignored
INFO - You can change the severity of this error message to warning using switch -change_error_to_warning "HDLCompiler:1821"


Take the following piece of code as an example:

module top (a,b,out);
  input [1:0] a,b;
  output [1:0] out;
  and and_inst[1:0][1:0] (out,a,b);

In this example, the 2-dimensional instantiation label and_inst[1:0][1:0] in the array of instances causes the 13.3 XST new parser to return the error "HDLCompiler:1821".

In ISE versions prior to 13.3, this code passes Synthesis and the 2-dimentional instantiation is interpreted as the following:

  and and_inst<0>1 (out[0],a[0],b[0]);
  and and_inst<1>1 (out[1],a[1],b[1]);

To resolve this error, instantiate individual gates separately. 

You can also set the XST switch below to change the error to a warning and return to the ISE 13.2 behavior.

-change_error_to_warning "HDLCompiler:1821"

AR# 44500
Date 03/11/2015
Status Active
Type Error Message
  • ISE Design Suite
  • ISE Design Suite - 13.3