We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44520

Timing -- Why am I seeing negative setup timing parameter in the timing report


I am seeing a negative value for a setup (Tdick) timing parameter in my timing report.

Why is this occurring?

For example:

Delay (setup path):     5.900ns (data path - clock path skew + uncertainty)
  Source:               c_counter_inst/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx5.i_dsp48e_wrap/i_primitive (DSP)
  Destination:          slow_pulse_cnt_12 (FF)
  Data Path Delay:      1.497ns (Levels of Logic = 0)
  Clock Path Skew:      -3.752ns (1.486 - 5.238)
  Source Clock:         clk400 rising at 8.888ns
  Destination Clock:    clk rising at 10.000ns
  Clock Uncertainty:    0.651ns

  Clock Uncertainty:          0.651ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.275ns
    Phase Error (PE):           0.509ns

  Maximum Data Path: c_counter_inst/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx5.i_dsp48e_wrap/i_primitive to slow_pulse_cnt_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    DSP48_X0Y32.P12      Tdspcko_PP            0.556   c_counter_inst/U0/i_synth/i_baseip.i_xbip_counter/i_dsp48.i_dsp/i_vx5.i_dsp48e_wrap/i_primitive
    SLICE_X53Y91.AX      net (fanout=2)        0.949   pulse_cnt_12_OBUF
    SLICE_X53Y91.CLK     Tdick                -0.008   slow_pulse_cnt<15>
    -------------------------------------------------  ---------------------------
    Total                                      1.497ns (0.548ns logic, 0.949ns route)
                                                       (36.6% logic, 63.4% route)


A negative value for a setup (Tdick) timing parameter is possible.
This happens because we do COMP base timing analysis and the minimum clock path can be slower than the data path within the COMP.

This can result in a negative setup time shown in the timing report.
AR# 44520
Date 02/17/2015
Status Active
Type General Article
  • Virtex-5
  • ISE Design Suite
Page Bookmarked