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AR# 44571

Virtex-4 FX Aurora - VHDL Clock Correction Module Modification

Description

The VHDL Virtex-4 FX Aurora version 3.1 contains a bug in the clock correction module: <component name>_standard_cc_module.vhd in the cc_manager directory.

In some configurations of the core, this can cause an incorrect amount of clock correction sequences to be transmitted. This shows up as an error on the receiver of the link partner.

NOTE: Thisbug does not exist in theVerilog version of the core.

Solution

To work around this problem, you must change lines 309 to 312 from the current clock correction to the correct clock correction as shown below.

Current

elsif(cc_count_r = "111111" ) then
DO_CC <= '1' after DLY;
else
DO_CC <= '0' after DLY;

Correct

elsif(cc_count_r /= "000000" ) then
DO_CC <= '1' after DLY;
elsif(cc_count_r = "000000") then
DO_CC <= '0' after DLY;

AR# 44571
Date Created 10/21/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
IP
  • Aurora 8B/10B Virtex-4 FX