We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44578

13.2 EDK, AXI_HWICAP - Data Read from AXI HWICAP Occurs One Clock Cycle too Early during Simulation


I am trying to simulatethe AXI HWICAP, however, it looks that the data read arrives ahead in one clock cycle. Is this a known issue? When can I expect a fix for it?


This is a known issue with UNISIM simulationmodel. The data read from the UNISIMmodel arrives one clock cycle tooearly. This affects Virtex-6 ICAP simulations only and does not impact the hardware functionality. This issue is planned to be fixed starting in the EDK 13.3 software release.
AR# 44578
Date Created 10/31/2011
Last Updated 05/19/2012
Status Archive
Type Known Issues
  • EDK - 13.2
  • EDK - 13.3
  • AXI Hardware ICAP