The XST parser of ISE 13.2design tools supports Verilog-2001, therefore,customers will not be able to get a proper outputfor $clog2 function. The Math function $clog2 was incorporated starting from Verilog-2005 (IEEE 1364-2005). Before that, clog2 could be realized as a Constant Function in Verilog 2001. Following is a samplefunction that can be used insteadfor the $clog2 function to get a proper output:
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
The above sample Verilog code with use of this function willnow become as follows:
module tb;
parameter A = clog2(325);
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
endmodule
This issue has been fixed as part of the 14.1 XST release. Also, It is in the road map to support System Verilog, which isa superset of Verilog-2005 using Xilinx tools and would include all advanced functionsmentioned in theLRM.