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AR# 44587

7 Series GTX/GTH/GTP Transceivers - RX OOB use modes

Description

Operation of OOB (electrical idle) for certain protocols at higher line rates such as PCIe (Gen1 and Gen2) and SATA is an advanced feature in 7 series GTX/GTH/GTP Transceivers.

This answer record addresses this feature in detail.

Solution

RX Termination for OOB

To use OOB, the following RX termination conditions need to be applied:

AC-coupled case: Termination voltage should be 800 mV or greater.
DC-coupled case: Termination voltage should be 900 mv or greater.

OOB <= 1.5 Gb/s

For OOB operating at a line rate of 1.5 Gb/s or below - please see the flow chart in figure 4 in the attachment to determine the frequency of the OOB clock.

f <=  linerate/(3 * max run length)

This requirement must be satisfied for the OOB to work correctly.

OOB > 1.5 Gb/s:

OOB operating at line rates > 1.5 Gb/s is an advanced feature. 

Operation for certain Protocols at higher line rates such as PCIe (Gen1 and Gen2) and SATA are addressed in the table below.

Protocol Operation
PCIe Gen1( See fig.  6)

Please see the flowchart for the algorithm to determine whether the RX is in electrical idle.

If a scrambler has not been used, do not use Electrical Idle for internal detect logic for Hold and Reset logic of DFE, Buffer, LPM and CDR. The user needs to verify received data to decide whether Electrical idle state is present or not (i.e qualification using incoming data is essential in this mode of operation).

If a scrambler is used, Electrical Idle can solely be used to determine whether RX is in Electrical idle.

PCIe Gen2 (see fig 7)

(note that other methods exist for this - see figure 8 and 9)

Please see flowchart for the algorithm to determine whether the RX is in electrical idle.

Do not use Electrical Idle for internal detect logic for Hold and Reset logic of DFE, Buffer, LPM and CDR.  The user needs to verify received data to decide whether Electrical idle state is present or not (i.e., qualification using incoming data is essential in this mode of operation).

SATA 1.5 Gb/s

(see fig. 4)

Please use the formula above to derive the appropriate OOB Clock.

SATA 3Gb/s

(see fig 5)

Please see flowchart for the algorithm to determine whether the RX is in electrical idle.

Do not use Electrical Idle for internal detect logic for Hold and Reset logic of DFE, Buffer, LPM and CDR. The user needs to verify received data to decide whether Electrical idle state is present or not (i.e., qualification using incoming data is essential in this mode of operation).

SATA 6Gb/s

(see fig. 5)

Please see flowchart for the algorithm to determine whether the RX is in electrical idle.

Do not use Electrical Idle for internal detect logic for Hold and Reset logic of DFE, Buffer, LPM and CDR.  The user needs to verify received data to decide whether Electrical idle state is present or not (i.e., qualification using incoming data is essential in this mode of operation).

PCIe Gen 3 or Gen2

(see fig. 8 and 9)

Please see flowchart for the algorithm to determine whether the RX is in electrical idle.

While entering and exiting Electrical idle, the EIOS detection must be used along with RXELECIDLE assertion to determine whether the RX is in Electrical idle.

Do not use Electrical Idle for internal detect logic for Hold and Reset logic of DFE, Buffer, LPM and CDR. The user needs to verify received data to decide whether Electrical idle state is present or not (i.e., qualification using incoming data is essential in this mode of operation).

 

The OOB circuit has two possible sources from which it can receive a clock. See figure 1 in attachment.

Attribute PCS_RSVD_ATTR[3] in GTX (this is called RX_OOB_CLK_CFG in the case of GTH/GTP transceivers) controls the source of oobclk. 

Setting PCS_RSVD_ATTR[3] or RX_OOB_CLK_CFG to 0 selects the sysclk. 

Setting this to 1 selects an alternative clock source from CLKRSVD[0] in the case of GTX (this is called SIGVALIDCLK in GTH/GTP). 

A divided down reference clock can be connected to the CLKRSVD[0] or SIGVALIDCLK pin, providing an alternative clock for the OOB circuit.

The port that controls the sysclk source is TXSYSCLKSEL. 

Setting this port to 1b0 selects the reference clock from the Channel PLL and setting this port to 1'b1 selects the reference clock from the Quad PLL.

The divided down clock(s) requires no special phase relationships between other clocks in the transceiver; however, there is a requirement of 50% duty cycle.

Figure 2 and 3 show the method for clock division.


Note: This OOB information and the use mode details for GTX/GTH are added to the 7 Series FPGA GTX/GTH Transceivers User Guide (UG476) v1.6. 

This is added to v1.4 of the 7 Series FPGA GTP Transceiver User Guide (UG482).

Attachments

Associated Attachments

Name File Size File Type
RX_OOB 229 KB PDF
AR# 44587
Date Created 10/09/2012
Last Updated 10/03/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7