UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44605

LogiCORE IP Serial RapidIO Gen2 v1.2 - Release Notes and Known Issues for ISE Design Suite 13.3

Description

This Release Note and Known Issues Answer Record is for the LogiCORE IP Serial RapidIO Gen2 v1.2, which was released in theISE 13.3 software and contains the following information:

  • Supported Devices
  • New Features
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide(XTP025).

Solution

Supported Devices

  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2L
  • Virtex-6 XC CXT/LXT/SXT/HXT

New Features

  • ISE 13.3 software support
  • Designed to RapidIO Interconnect Specification v2.2
  • AXI Interfaces
  • Per-lane speeds of 1.25, 2.5, 3.125, 5.0, and 6.25 Gbaud
  • 1x, 2x, or 4x operation

Known Issues

  • (Xilinx Answer 44298) LogiCORE IP Serial RapidIO Gen2 v1.2 - Hardware Validation Status
  • (Xilinx Answer 44299) LogiCORE IP Serial RapidIO Gen2 v1.2 - Timing failure when implementing Messaging/User Defined Ports
  • (Xilinx Answer 44300) LogiCORE IP Serial RapidIO Gen2 v1.2 - Link Requests (LREQ) not sent before going into the Fatal Error state
  • (Xilinx Answer 44301) LogiCORE IP Serial RapidIO Gen2 v1.2 - Asserting link_reset does not reset the core
  • (Xilinx Answer 44302) LogiCORE IP Serial RapidIO Gen2 v1.2 - LREQ-reset control symbols are not transmitted back-to-back when in IDLE2
  • (Xilinx Answer 44304) LogiCORE IP Serial RapidIO Gen2 v1.2 - Software Assisted Error Recovery not supported
  • (Xilinx Answer 44305) LogiCORE IP Serial RapidIO Gen2 v1.2 - Read of the Assembly Info Register returns incorrect value for assembly revision
  • (Xilinx Answer 44461) LogiCORE IP Serial RapidIO Gen2 v1.2 - Port might not initialize correctly when a cfg write causes the port to re-initialize
  • (Xilinx Answer 44718) LogiCORE IP Serial RapidIO Gen2 v1.2 - Incorrect IREQ and TRESP SourceID field connection in the example design
  • (Xilinx Answer 43482)7 Series GTX Transceivers - Reset requirements upon configuration
  • (Xilinx Answer 45488)LogiCORE IP Serial RapidIO Gen2 v1.2 - When a forced re-initialization occurs, the core does not restart the IDLE sequence selection
  • (Xilinx Answer 45490) LogiCORE IP Serial RapidIO Gen2 v1.2 - ALIGNS might not be properly detected when using the chanbondseq signal from the GTX
  • (Xilinx Answer 45492)LogiCORE IP Serial RapidIO Gen2 v1.2 - Does the core support XC7K160T-1FBG676?
  • (Xilinx Answer 45493)LogiCORE IP Serial RapidIO Gen2 v1.2 - The core does not lose sync when an invalid character is received
  • (Xilinx Answer 45494)LogiCORE IP Serial RapidIO Gen2 v1.2 - The core sends packets with overlapping ackIDs when port_init drops
  • (Xilinx Answer 45056)LogiCORE IP Serial RapidIO Gen2 v1.2 - Idle_selected signal is Hi-Z in simulation
  • (Xilinx Answer 45495) LogiCORE IP Serial RapidIO Gen2 v1.2 - The core unexpectedly trains down when ALIGN errors occur
  • (Xilinx Answer 43339)7 Series FPGA GTX Transceiver - Software Use Model Changes

Revision History
02/09/2012 - Added Answer Record 43339
01/09/2012 - Updated; added Answer Records 43482, 45488, 45490, 45492, 45493, 45494, 45056, and 45495
10/26/2011 - Initial release

AR# 44605
Date Created 10/18/2011
Last Updated 05/19/2012
Status Active
Type Release Notes
IP
  • Serial RapidIO