UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4461

2.1i: Constraint Editor: Can't find Clock Enable net when All Nets is selected.

Description

General Description:

In the TPTHRU dialog, the net A_EQ_B doesn't show up,

but view the design in FPGA Editor, the net is listed.

Solution

The net is connected to the CLK_EN pin (clock enable),

which is not listed under All Nets

This will be fixed in a future release of the software or

service pack.

AR# 4461
Date Created 08/31/2007
Last Updated 01/18/2010
Status Archive
Type General Article