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AR# 44635

7 Series - EMCCLK considerations to ensure the FPGA completes the startup sequence

Description

At the end of configuration, when the FPGA transitions from Configuration Mode to User Mode, all of the multi-purpose I/Os transition from the default (power-on setting) IOSTANDARD to the user-defined IOSTANDARD during the STARTUP sequence. 

As the FPGA switches from Configuration Mode to User Mode, if the multi-purpose I/O bank_14 voltage is undefined in the user design, the EMCCLK is effectively turned OFF in the middle of the STARTUP sequence, and the STARTUP sequence stops at GTS.

How do I work around this issue?

Solution

EMCCLK is included in bank 14, which has many dual purpose pins used for configuration. The bank_14 voltage needs to be defined for EMCCLK usage to be supported.

The EMCCLK pin is enabled with the following write_bitstream property:

BITSTREAM.CONFIG.EXTMASTERCCLK_EN | Div-1, Div-2, Div-4, Div-8.

When setting this property, a command is inserted into the bitstream that switches the configuration clock source from the internal oscillator to EMCCLK.


To ensure that the EMCCLK input path remains enabled through the startup transition as the configuration clock source, at least one of the following implementations must be used:

  1. If EMCCLK is not used in the design, then another I/O in the same bank (bank_14) must be used and have its IOSTANDARD defined. The voltage defined is applied to EMCCLK.
  2. If EMCCLK is used in the design, then it must have its IOSTANDARD defined.
  3. If neither of the above conditions are met, then Vivado checks if the CONFIG_VOLTAGE constraint is defined (CONFIG_VOLTAGE 1.5, 1.8, 2.5, 3.3). If it is defined then there are no other requirements.


Linked Answer Records

Associated Answer Records

AR# 44635
Date Created 10/19/2011
Last Updated 03/30/2016
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
Tools
  • Vivado Design Suite - 2015.4