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AR# 44635 7 Series - 13.x ISE BitGen - EMCCLK Considerations to ensure that the FPGA Completes Startup Sequence

Description

When I use EMCCLK as my configuration clock source,I see that my device does not complete the configuration startup sequence. How do I work around this issue?

Solution

To work around this issue in the 13.x software, you must ensure that one of the following is implemented:

  1. The EMCCLK pin is used as an I/O in the design after configuration.
  2. At least one I/O isinstantiated and its standard definedin the design residingin the I/O Bank 14 where the EMCCLK pin is placed.

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AR# 44635
Date Created 11/01/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
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