^
Advanced Search

AR# 44643 7 Series Integrated Block for PCI Express - Signals cfg_pm_halt_l1, cfg_pm_force_state[1:0] seem to imply APSM L1 is supported

Description

Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

The 7 Series FPGAs Integrated Block for PCI Express User Guide (UG477) describes signals named cfg_pm_halt_l1 and cfg_pm_force_state[1:0] that seem to indicate ASPM is supported. Is ASPM L1 supported?

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution

No, only ASPM L0s is supported as stated the Power Management section of the "Designing with the Core" section of the user guide.

Revision History
12/06/2011 - Added version resolved reference to AR 40469
10/26/2011 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
40469 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions N/A N/A

Actions

AR# 44643
Date Created 10/19/2011
Last Updated 05/22/2012
Status Active
Type Known Issues
Feed Back