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AR# 44648

13.3 Kintex-7, IBERT GTX - QPLLREFCLKSEL always selects REFCLK0


When I generate a Kintex-7 FPGA GTX IBERT design in 13.3 using the QPLL, QPLLREFCLKSEL always selects REFCLK0 even if you select REFCLK1 in the Wizard.


To work around this issue, manually changing the QPLLREFCLKSEL port to the correct value will be necessary so the proper reference clock is used by the design.

Follow these steps to make the necessary change:

  1. Click on the "Ports" tab in the IBERT GUI in theChipScope Analyzer and click the "Common" radio button.
  2. Find the port in the COMMON block called QPLLREFCLKSEL.
  3. Set the value of this port to 0x2, this selects REFCLK1.
  4. Reset the QUAD after changing the value of QPLLREFCLKSEL.

At this point, it is possible that the QPLL still shows that the QPLL is not locked, but the GTX should now show LINKED. This is a known issue in 13.3 which is caused by the IBERT Core not reading the currentvalue of the QPLL locked status periodically. Follow the steps in (Xilinx Answer 44649) which details how to force IBERT to read the proper status of the QPLL Locked field.

This is a known issue in 13.3 and is scheduled to be fixed in 13.4.

AR# 44648
Date Created 10/27/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
  • Kintex-7
  • ChipScope Pro - 13.3