The PHYCTLEMPTY path might produce a timing error at the higher supported frequencies similar to the following:
1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
Minimum period is 1.315ns.
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Slack (setup path): -0.243ns (requirement - (data path - clock path skew + uncertainty))
Source: u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i (OTHER)
Destination: u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.ddr_phy_4lanes/phy_control_i (OTHER)
Requirement: 1.072ns
Data Path Delay: 1.012ns (Levels of Logic = 0)
Clock Path Skew: -0.258ns (0.378 - 0.636)
Source Clock: u_mig_7series_v1_3/mem_refclk rising at 0.000ns
Destination Clock: u_mig_7series_v1_3/mem_refclk rising at 1.072ns
Clock Uncertainty: 0.045ns
Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.054ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i to u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.ddr_phy_4lanes/phy_control_i
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------------------- -------------------
PHY_CONTROL_X1Y6.PHYCTLEMPTY Tpctcko_EMP 0.488 u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i
u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.ddr_phy_4lanes/phy_control_i
PHY_CONTROL_X1Y5.PHYCTLMSTREMPTY net (fanout=2) 0.525 u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/phy_ctl_empty<0>
PHY_CONTROL_X1Y5.MEMREFCLK Tpctckd_EMP -0.001 u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.ddr_phy_4lanes/phy_control_i
u_mig_7series_v1_3/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.ddr_phy_4lanes/phy_control_i
------------------------------------------------------------- ---------------------------
Total 1.012ns (0.487ns logic, 0.525ns route)
(48.1% logic, 51.9% route)
The timing failures occur at the highest frequencies in each speed grade when a memory controller spans 2-3 banks.This occurs because the designated 'master bank' for the phy_control_block is always placed in the top most bank.However, the 'master bank' should instead be located in the bank with the PLL and the address/control.
To resolve the timing errors, locate the following localparam in the 'user_design/rtl/phy_ddr_mc_phy.v' module:
localparam MASTER_PHY_CTL = 0;
For customers using 3 banks, change this to a 1. For customers using 1 bank, leave this at 0. For customers using 2 banks, set this to either 0 or 1 depending on whether the address/control bank is located physically above or below the data bank.