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AR# 44665 AXI Bridge for PCI Express - No DRC for overrunning the AXI memory mapped space

Description


Version Found: 1.00.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

The AXI Bridge for PCI Express Core does not have a DRC when the BAR range overruns the AXI memory space. For example, the following condition should issue a DRC error:

(Please assume unsigned arithmetic)
C_PCIEBAR2AXIBAR_# + 2^ C_PCIBAR_LEN_# > 0xFFFF_FFFF

NOTE: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution


If the condition above is met, memory writes will not reach the expected AXI locations and might write to other valid areas of the memory mapped space. Memory reads will either result in Completion TLPs with Unsupported Request, or with data from other valid areas of the memory mapped space.

Revision History:
11/07/2011 - Updated for 13.3
10/24/2011 - Initial Release

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AR# 44665
Date Created 10/31/2011
Last Updated 11/22/2011
Status Active
Type
IP
  • AXI PCI Express (PCIe)
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