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AR# 44695 MIG 7 Series v1.3 - sys_rst is not validated properly using the "Verify Pin Changes and Update Design" flow

Description

The sys_rst signal may not be validated properly using the "Verify Pin Changes and Update Design" flow. A pin site and/or incorrect IOSTANDARD may be generated in the UCF if imported mig.prj file was originally created using "Fixed Pin Out" mode.

Solution

If the mig.prj file was originally created using the "Fixed Pin Out" mode and a pin was selected for sys_rst, then that same pin site and IOSTANDARD will be used after generating the updated design and UCF using the "Verify Pin Changes and Update Design" flow. This may still occur even if a pin location was not selected during the "Verify Pin Changes and Update Design" flow.

Customers can work around this by manually changing the pin location and IOSTANDARD in the newly generated UCF file.This will be fixed in the MIG7 Series v1.4 13.4 release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Actions

AR# 44695
Date Created 10/25/2011
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Virtex-7
  • Kintex-7
IP
  • MIG 7 Series
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