If you are using a PLL in the INTERNAL mode, make sure to use the PLL for frequency synthesis only. The PLL does not perform any phase-alignment or deskewing of the clock. Because of this, the phase relationship between the two clocks is not guaranteed and cannot be determined.
If the design requires that a known phase relationship be used with the PLL, use of the INTERNAL compensation mode is not recommended. In this case, use either SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS, which have a known phase relationship between the input and output clock ports of the PLL.