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AR# 44717

Zynq-7000 EMIO statuses

Description

1) What is the state of the EMIO pins when the FPGA is not programmed?

2) What is the state of the EMIO pins when the FPGA is being programmed?

Solution

1) What is the state of the EMIO pins when the FPGA is not programmed.

All inputs (PL to PS) are held at 0. Outputs (PL from PS) are also 0, but the PL is not programmed so there is no logic to use it.

2) What is the state of the EMIO pins when the FPGA is being programmed?

All inputs (PL to PS) are held at 0.

AR# 44717
Date Created 11/13/2012
Last Updated 11/13/2012
Status Active
Type General Article
Devices
  • Zynq-7000