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AR# 44747

14.7 Virtex-6 Place - ERROR:Place:907 - Placer failed to find a location for a regional clock load.

Description

My design is failing with the following error:

ERROR:Place:907 - Placer failed to find a location for a regional clock load. It is partially caused by user constraint on following component group: COMP: "RX_CHAN[1].rx_channel_1/rx_auto_gate_1/Mmux_CLKSEL_OUT1" COMP: "RX_CHAN[1].rx_channel_1/rx_auto_gate_1/Mmux_CLKSEL_OUT1" COMP: "RX_CHAN[1].rx_channel_1/rx_auto_gate_1/Mmux_CLKSEL_OUT1" COMP: "RX_CHAN[1].rx_channel_1/rx_auto_gate_1/Mmux_CLKSEL_OUT1" To debug your design with partially routed design, please try to allow map/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

When I set the variable mentioned in the error message, the design runs successfully with no routing issues.


Why does this error occur?

Solution

The Slice component that is mentioned in the error message multiple times contains LUTs that have three different BUFR nets as inputs. 

The three BUFRs are LOC'd to three consecutive clock regions.

Although the clock placer was unable to find a solution, the slice component can be legally placed in the middle clock region of the three.

As this is a low frequency use case, this will remain a limitation in ISE Design Suite.

In the meantime, the work around is to override the error with the XIL_PAR_DEBUG_IOCLKPLACER variable.

For general information about setting ISE environment variables, see (Xilinx Answer 11630).

 

AR# 44747
Date Created 10/27/2011
Last Updated 03/02/2015
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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  • Virtex-6QL
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Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
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  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
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  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
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