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AR# 44801

Virtex-6, 13.3, GTX IBERT - Right side GTX transceivers do not link

Description

For the Virtex-6 GTX IBERT core in the ISE Design Suite 13.3, there is a known issue thatcan cause the right side GTX transceivers to not link.

Solution

If the CORE Generatorproject options are set to Verilogwhenyou generate the Virtex-6 GTX IBERT core, the right side GTX transceivers will not work.This issue is due to refclk signals on the right side transceivers that are not declared in the VerilogHDL code.

To work around this issue, change the CORE Generator project options to VHDL for the programming language and regenerate the IBERT core.

This is a known issue that affects the Virtex-6 GTX IBERT core in ISE Design Suite13.3 and will be fixed in the ISE Design Suite13.4 release.

AR# 44801
Date Created 11/03/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 CXT
Tools
  • ChipScope Pro - 13.3