We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44814

ML605 - SO DIMM shipped with newer version


Newer Virtex-6 FPGA ML605 Evaluation Kits ship with1 GB DIMMs versus the 512 MB DIMMs on previous boards. This change is due to the discontinuation of the 512 MB DIMMs by the memory manufacturer.

ML605 boards with 1 GB DIMMs require application of the solution detailed below.


The ML605 boards shipped with 1 GB DIMMs require application of the following solution. This allows the 1 GB DIMMs to work as the 512 MB DIMM. All previous and future designs will work across boards built with 512 MB and 1 GB DIMMs.

The solution needed is to tie the Row Address 13 pin to a logic high on designs using MPMC or MIG.

The 512 MB DIMMs are MT4JSF6464HY-1G1B1
The 1 GB DIMMs on the newer ML605 boards are MT4JSF12864HZ-1G4D1

All of the data sheets can be found on the ML605 web page: http://www.xilinx.com/ml605

Note: The Row Address 13 pin is not connected to the memory devices on the 512 MB DIMMs, so it has no effect on boards shipped with 512 MB DIMMs.
When the Row Address 13 pin is driven high on the 1 GB DIMMs, it makes half of the memory available, that is, the resulting memory is half the original size.

The next procedure describes how to modify any existing and/or future EDK designs so that they can operate with 1 GB DIMMs. The concept is the same for any MIG based design.


1. Add the following to the port section of the MHS file:
PORT fpga_0_DDR2_SDRAM_DIMM0_DDR2_RowAddr_pin_13 = fpga_0_DDR2_SDRAM_DIMM0_DDR2_RowAddr_pin_13, DIR = O

2. Add this core to the very bottom of the MHS file:

BEGIN util_reduced_logic
PORT Op1 = 0b0 & 0b0
PORT Res = fpga_0_DDR2_SDRAM_DIMM0_DDR2_RowAddr_pin_13

3. Add the following to the UCF file:

Net fpga_0_DDR2_SDRAM_DIMM0_DDR2_RowAddr_pin_13 LOC=J15 |IOSTANDARD = SSTL15;

Note: The solution above allows the designs for 512 MB DIMM to work for 1 GB DIMM, it makes half of the memory unavailable. To access full 1 GB memory, the Base Address of MPMC instance needs to be modified to 1 GB memory size.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34836 Virtex-6 FPGA ML605 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 44814
Date Created 04/24/2012
Last Updated 03/04/2013
Status Active
Type General Article
Boards & Kits
  • Virtex-6 FPGA ML605 Evaluation Kit