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AR# 44854 MIG 7 Series v1.3 DDR3 - Certain configurations cause designs to fail calibration in simulation

Description

In certain configurations, MIG 7 Series v1.3 DDR3 SDRAM designs stick in calibration during simulations for all scenarios with "Phy to Controller Clock Ratio" of 1 (nCK_PER_CLK = 2), and also in certain cases for "Phy to Controller Clock Ratio" of 4 (nCK_PER_CLK = 4). These problems could affect hardware simulations and is a result of an issue in one of the RTL parameters.

Solution

To fix the issue, the PHY_DISABLE_SEQ_MATCH parameter needs to change from "FALSE" to "TRUE" in the ddr_mc_phy_wrapper module located in <component name>/user_design/rtl/phy folder.

This is scheduled to be fixed in the 13.4 MIG v1.4 release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Actions

AR# 44854
Date Created 11/07/2011
Last Updated 05/22/2012
Status Active
Type Known Issues
Devices
  • Virtex-7
  • Kintex-7
IP
  • MIG 7 Series
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