UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44893

LogiCORE IP Tri-Mode Ethernet MAC v5.1 - Base Address and High Address Restriction in the Block Level when Generating the Core with axi-lite

Description

When generating the LogiCORE IP Tri-Mode Ethernet MAC v5.1 core with axi-lite, the axi-lite to IPIF shim in the block level has a defined base address which defaults to zero. Another parameter is also available to allow the high address to be set. There is no mechanism in the core to make sure no illegal values are set for these addresses (for instance,high address lower than base address, etc.).

Solution

This issue will be fixed in LogiCORE IP Tri-Mode Ethernet MAC v5.2. The fix for this issue for the LogiCORE IP Tri-Mode Ethernet MAC v5.1 core is provided with the Rev2 update available in (Xilinx Answer 40624). The patch in the Rev2 update generates high address internally based on the value of the base_address, thus leaving little scope for error and ensuring the high address has the correct value.

Revision History:

11/07/2011 - Initial Release

AR# 44893
Date Created 06/04/2012
Last Updated 06/04/2012
Status Archive
Type Known Issues
IP
  • Tri-Mode Ethernet MAC