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Differences may be seen between the ISE Timing report and Vivado Timing report for the same design.
This is expected since Place and Route are different in ISE and Vivado.
In addition, the ISE and Vivado timing engines work differently, which results in differences between the timing reports.
What are the differences between the TRCE/Timing Analyzer Results (TWX/TWR) and the report_timing/report_timing_summary results?
There are many differences between TRCE static timing engine (STA) and Vivado STA engines.
Below is a list of some of these differences:
TRCE is component based - all of the timing delays are related to the pins of the component (SLICE, etc). However, Vivado STA is bel (basic element) based, which means that the timing delays are related to the pins of the basic element - e.g. FDCE, FDPE, FDRE, FDSE inside the slice.
In TRCE, exception paths are reported under the exception type constraints (FROM:TO) and not under fundamental constraints (PERIOD). In Vivado STA exception paths will be reported under the fundamental constraints only (create_clock, etc.)
By default, TRCE reports the three worst-case paths per constraint, but Vivado STA will report the worst-case for the design.
By default, TRCE treats all clocks as asynchronous unless they are constrained to be synchronous. Vivado STA treats all clocks as synchronous unless they are constrained to be asynchronous (set_false_path, set_clock_groups, etc.)
TRCE and Vivado STA calculate the Total System Jitter on input and output paths differently. See (Xilinx Answer 59944).