UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44918

Vivado Constraints - UCF versus XDC (SDC)

Description

What are the differences between UCF and XDC constraints/commands?

Solution

There are many differences between UCF constraints and XDC commands. Below are a list of some of these differences:

  • UCF constraints are defining the internal delays of the FPGA, but XDC commands are defining the internal and external relationships between the clock and the upstream/downstream devices for the I/Os
  • UCF constraints are timing group (TNM, TNM_NET, TIMEGRP) based, but the XDC commands are instance (get_cell), net (get_net), pin (get_pin), and port (get_port) based
  • UCF constraints define the requirements as a maximum delay, but XDC commands can define both the minimum and maximum delay for a given path

 

AR# 44918
Date Created 04/30/2012
Last Updated 08/07/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2012.1
  • Vivado Design Suite - 2013.2
  • Vivado Design Suite - 2013.1
  • More
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite - 2012.3
  • Vivado Design Suite - 2012.2
  • Less