I want to add my CORE Generator IP cores to the "design_lib" VHDL Library within myISE tools project, but it does not seem possible.
I opened the "library" tab in theISE tools and attempted to drag and drop my XCO files into the library, but this is not permitted. I can do this without issue for VHDL files.
Also, when I right-click on the XCO file, the "Move to Library" option is greyed out. Why is this feature not permitted in theISE design tools?
This optionis not permitted in ISE design suite projects becauseXCO are not VHDL files and this feature is predominantly created for HDL files. This is not an option that will be incorporated into the Xilinx ISE tools solution, but it might be considered for the next generation solution at a future date.
For now, the work-around is to add the IP core after generation by adding the VHDL wrapper and NGC files to the project. The VHDL file can then be moved into the chosen library in the same manneras all other VHDL files.
NOTE: You might receive an"Unassigned User Library Modules" messageafter performing the above work-around. To avoid this, ensure the references to this library are correct in your upper levels of hierarchy.