AR# 44929
AXI Bridge for PCI Express - Reading from the Control Registers in the Bridge Returns Incorrect Values
Description
Accessing the Control Registers of the AXI bridge for PCI Express can result in corrupt data. This will happen if the interconnect is not connected to the same clock as the output clock from the bridge.Solution
To work around this issue, add following parameter to the axi_pcie bridge instantiation in the Microprocessor Hardware Specification (MHS) file:
parameter C_INTERCONNECT_S_AXI_CTL_IS_ACLK_ASYNC = 1
This can also be changed through the interface with the following checkbox:
Revision History:
11/28/2011 - Added image
11/09/2011 - Initial release
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Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 44972 | AXI Bridge for PCI Express FAQ | N/A | N/A |
| AR# 44929 | |
|---|---|
| Date | 08/26/2013 |
| Status | Active |
| Type | General Article |
| IP |
|