The BUSY pin no longer exists in the Virtex-7 FPGA, Kintex-7 FPGA, and Artix-7 FPGAfor the SelectMap interface. Also, the Internal Configuration Access Port (ICAPE2) component no longer includes the BUSY pin.
The BUSY pin was removedbecause it is used only during readback for previous Virtex family. Starting with the7 series, readback data is valid deterministically three clock cycles after the configuration interface pin, or CS, is asserted during readback.