In both the 7 Series XADC and UltraScale SYSMON, there is a single dedicated analog input pair (VP/VN) and up to 16 auxiliary analog inputs in the I/O banks.
The Analog inputs can be configured in either Unipolar or Bi-polar mode.
When unipolar operation is enabled, the differential analog inputs (VP and VN) have an input range of 0V to 1.0V.
In this mode, the voltage on VP or Vauxp (measured with respect to VN or Vauxn) must always be positive.
Vn/Vauxn can be connected to either GNDADC or a common mode signal.
The common mode signal on VN can vary from 0V to +0.5V (measured with respect to GNDADC).
Because the differential input range is from 0V to 1.0V (VP to VN), the maximum signal on VP is 1.5V
When bipolar operation is enabled, the differential analog input (VP VN) can have a maximum input range of 0.5V.
The common mode or reference voltage should not exceed 0.5V.
It is also possible to drive the analog input with true differential signals. In this case VN and VP can swing positive and negative relative to a common mode or reference voltage.The differential input can be in the range 0.5V so the common mode can be in the range 0.25V to 0.75V.
Maximum and Minimum Input Voltages:
The documentation for 7 series and UltraScale states that the input voltage can exceed VCCADC (1.8V) or go below GNDADC by as much as 100 mV without damage to the XADC/SYSMON.
A current-limiting resistor of at least 100 should be placed in series with the analog inputs to limit the current to 1 mA.
The resistors in the Anti-Aliasing filter normally satisfy this requirement.
It is not enough to take this recommendation in isolation.
Care should be taken when the VAUX inputs are used.
The VAUX inputs occupy I/O sites in the SelectIO banks. The clamp diode to VCCO of the bank is always present in the input regardless of whether it is used as an analog input or a digital I/O.
The first case is when the VCCO of the bank is greater than or equal to VCCADC.
In this case the input voltage must be in the range -0.1V to VCCADC+0.1V without risking damage to the XADC or SYSMON.
The second case is when the VCCO of the bank containing the VAUX input is lower than VCCADC.
In this case the minimum input voltage must not exceed GNDADC -0.1V to ensure the XADC or SYSMON is not damaged.
The maximum input voltage must satisfy the recommended Vin Spec of VCCO + 0.2V for the IO.
For guidelines on how to properly drive the analog inputs please refer to XAPP795 Driving the Xilinx Analog-to-Digital Converterhttp://www.xilinx.com/support/documentation/application_notes/xapp795-driving-xadc.pdf