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AR# 44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions

Description

This Release Notes and Known Issues Answer Record is for the AXI Bridge for PCI Express, which was first released in EDK 13.2 and contains the following information:

  • General Information
  • Supported Devices
  • Resolved Issues
  • Known Issues

Solution

General Information

The ISE Design Suite 14.5 release contains the v1.07.a core.

For release notes on standalone Xilinx PCI Express Block cores, see the IP Release Notes Guide.

All PCI Express Documents can be found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express.htm

For High Speed transceivers known issues and answer record list, see (Xilinx Answer 37179)

For AXI Bridge for PCI Express v2.0 core release notes, see (Xilinx Answer 54646)

Supported Devices

Note: For the previous version "New Features" and "Supported Devices", see the change_log.html located in the "$XILINX_EDK/hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v4_06_a\doc\html\" directory, or reference the data sheet:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express.htm#189513

Known Issues

This table correlates the core version to the first ISE design tools release in which it was included.

Core Version
ISE / Vivado Version
v1.07.a ISE 14.5
v1.06.a ISE 14.4 / Vivado 2012.4
v1.05.a  ISE 14.3 / Vivado 2012.3
v1.04.a ISE 14.2
v1.03.a
ISE 14.1
v1.02.a
ISE 13.4
v1.01.a
ISE 13.3
v1.00.a
ISE 13.2


The following table provides known issues for the AXI interface version of the AXI Bridge for PCI Express.

Note: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 55348) Interrupt Decode Register gets wrongly set when performing DMA with ASPM enabled in RC mode v1.07.a Not Resolved Yet
(Xilinx Answer 55349) AXI Bridge becomes unresponsive when performing DMA with ASPM enabled in RC mode v1.06.a Not Resolved Yet
(Xilinx Answer 55350) The core in EP mode fails with corrupted data written to memory when configured for x4Gen2 on Zynq devices v1.06.a v1.07.a
(Xilinx Answer 55351) Missing completion for Memory Read when configured as RC x4Gen2 on Zynq devices v1.06.a v1.07.a
(Xilinx Answer 53740) (ISE 14.4 / 2012.4) - No Clock Output on TXOUTCLK at Cold Temperature v1.06.a v1.07.a
(Xilinx Answer 53511) (Vivado 2012.3) - [IP_Flow 19_1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0' v1.05.a v1.06.a
(Xilinx Answer 53114) Incorrect UCF constraint generated when using 250 MHz reference clock v1.05.a v1.06.a
(Xilinx Answer 52688) Completion TLP not generated when configured as Root Complex on Zynq devices v1.04.a v1.05.a
(Xilinx Answer 52687) Default value of C_PCIEBAR2AXIBAR_*_SEC v1.04.a v1.05.a
(Xilinx Answer 52686) The core replies with incorrect data when reading Configuration Space for invalid Devices v1.04.a v1.05.a
(Xilinx Answer 52685) Link trains down due to incoming MWr packets v1.04.a v1.05.a
(Xilinx Answer 52684) Incorrect MSI Message routing in 128-bit mode operation v1.04.a v1.05.a
(Xilinx Answer 52679) Directed Link Change is not supported v1.04.a v1.05.a
(Xilinx Answer 52678) Completion Payload greater than MPS Value v1.04.a v1.05.a
(Xilinx Answer 52677) The core runs into Fatal Error during multiple MRds upstream v1.04.a v1.05.a
(Xilinx Answer 50633) Root Port Implementation does byte swap to the completion packet for a configuration read issued to an Endpoint device v1.03.a v1.05.a
(Xilinx Answer 50634) Memory Write to address 0x0000_0000 is treated as an MSI Request in Gen1X8 and Gen2X4 Endpoint configuration v1.03.a v1.05.a
(Xilinx Answer 46622)
 Large AXI initiated read request may cause pre-mature completion timeout
v1.02.a
v1.04.a
(Xilinx Answer 44665)
 No DRC for overrunning the AXI memory mapped space
v1.00.a
Not Resolved Yet
(Xilinx Answer 44700)
 C_PCIEBAR2AXIBAR_# restriction on bits lower than C_PCIBAR_LEN_#
v1.00.a
Not Resolved Yet
(Xilinx Answer 43709)
 The GUI does not allow C_AXIBAR2PCIEBAR_# to accept 64-bit address values
v1.00.a
Not Resolved Yet
(Xilinx Answer 46638)
 No response to zero length memory read requests when configured as x4 gen2 or x8 gen1
v1.02.a
v1.03a
(Xilinx Answer 46647)
 Zero-length write transactions on the AXI Slave port cause the AXI interface to hang
v1.02.a
v1.03a
(Xilinx Answer 46623)
 Using 128-bit Interface (x8 Gen 1 or x4 Gen 2), an array size mismatch occurs on Completions with Data
v1.02.a
v1.03a
(Xilinx Answer 46649)
 Spartan-6 32-bit interface AXI Initiated Write Request Creates Malformed TLP
v1.02.a
v1.03a
(Xilinx Answer 46646)
 In Root Port configuration memory read TLP completions can be dropped if both configuration and memory read TLPs are outstanding
v1.02.a
v1.03a
(Xilinx Answer 46624)
 Root Port Configuration BAR miss is passed to AXI MM Bridge
v1.02.a
v1.03a
(Xilinx Answer 46563)
 Selecting 128-bit Interface Width gives ERROR:HDLCompiler:410 error
v1.02.a
v1.03a
(Xilinx Answer 46273)
 Kintex-7 simulation will not link train when C_PCIE_USE_MODE = 1.0 (IES)
v1.02.a
v1.03a
(Xilinx Answer 46235)
 x8 gen1 and x4 gen2 do not have a DRC to ensure a 128-bit interface
v1.02.a
v1.03a
(Xilinx Answer 46100)
 x8 gen 1 for Virtex-6 should issue a DRC error
v1.02.a
v1.03a
(Xilinx Answer 46685)
 Support for Virtex-7 in 13.4
v1.02.a
v1.03a
(Xilinx Answer 45988)
 1 DW Write Transactions on the AXI4 Slave Interface create Malformed TLPs when using a 32-bit AXI Data Width
v1.00.a
v1.03a
(Xilinx Answer 44074)
 Enumerating multiple 64-bit BARs to 32-bit BARs might cause issues for the 64-bit AXI data width
v1.00.a
v1.03a
(Xilinx Answer 44211)
 MSI interrupts only supports a single vector
v1.00.a
v1.03a
(Xilinx Answer 45234)
 64-bit TLPs are generated when requested address is less than 4GB
v1.00.a
v1.03a
(Xilinx Answer 42642)
 AXI interconnect frequency cannot be determined when using the axi_aclk_out clock
v1.00.a
v1.02a
(Xilinx Answer 45078)
 Integer overflow error when simulating in NCSim
v1.00.a
v1.02a
(Xilinx Answer 43681)
 Root Complex option does not have a DRC
v1.00.a
v1.01.a
(Xilinx Answer 43708)
 Changing C_AXIBAR_NUM does not grey out unused C_AXIBAR_#
v1.00.a
v1.01.a
(Xilinx Answer 43313)
 m_axi_arlockand m_axi_arcache are connected to the AXI write address channel
v1.00.a
v1.01.a
(Xilinx Answer 43263)
 AXI data width does not have device dependent DRC
v1.00.a
v1.01.a
(Xilinx Answer 43805)
 Mastering on the AXI-lite interconnect with a 64-bit AXI data width interface causes DECERR
v1.00.a
v1.01.a
(Xilinx Answer 44976)
 Writes transactions to AXI4-lite Control Interface result in SLVERR
v1.00.a
v1.01.a


For further help using the AXI Bridge for PCI Express, refer to (Xilinx Answer 44972).

Revision History
04/03/2013 - Updated for ISE 14.5 release
01/21/2013 - Added (Xilinx Answer 53740)
12/18/2012 - Updated for 14.4/2012.4 design tools release
11/29/2012 - Added (Xilinx Answer 53114)
10/23/2012 - Updated for 14.3 / 2012.3 design tools release
07/25/2012 - Updated for 14.2 design tools release
05/08/2012 - Updated for 14.1 design tools release
03/06/2012 - Added 46685
03/05/2012 - Added 46638, 46647, 46623, 46649, 46646, 46622, 46624, 46563
02/29/2012 - Updated the transceiver constraint
02/27/2012 - Added 46563
02/15/2012 - Added 46100, 46235, 46273
01/24/2012 - Added 45988
01/18/2012 - Updated for ISE 13.4 software and v1.02a
12/01/2011 - Added 45234
11/27/2011 - Added 43709 and 44976
11/21/2011 - Initial Release

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
46685 AXI Bridge for PCI Express - Support for Virtex-7 FPGA in 13.4 N/A N/A
46649 AXI Bridge for PCI Express - Spartan-6 32-bit inteface AXI Initiated Write Request Creates Malformed TLP N/A N/A
46647 AXI Bridge for PCI Express - zero-length write transactions on the AXI Slave port cause the AXI interface to hang N/A N/A
46646 AXI Bridge for PCI Express - In Root Port mode, memory read completion can be lost if Memory Read TLPs and Configuration TLPs are outstanding at the same time N/A N/A
46638 AXI Bridge for PCI Express - The bridge does not respond to memory read requests with a length of 0 when configured as x4 gen2 or x8 gen1 N/A N/A
46273 AXI Bridge for PCI Express - Kintex-7 simulation will not link train when C_PCIE_USE_MODE = 1.0 (IES) N/A N/A
46235 AXI Bridge for PCI Express - x8 gen1 and x4 gen2 do not have a DRC to ensure a 128-bit interface N/A N/A
45988 AXI Bridge for PCI Express - 1 DW Write Transactions on the AXI4 Slave interface create malformed TLPs when using a 32-bit AXI data width N/A N/A
45234 AXI Bridge for PCI Express - 64-bit TLPs are generated when requested address is less than 4GB N/A N/A
45078 AXI Bridge for PCI Express - Integer overflow error when simulating in NCSim N/A N/A
44976 AXI Bridge for PCI Express - Writes transactions to AXI4-lite Control Interface result in SLVERR N/A N/A
44972 AXI Bridge for PCI Express FAQ N/A N/A
44700 AXI Bridge for PCI Express - C_PCIEBAR2AXIBAR_# restriction on bits lower than C_PCIBAR_LEN_# N/A N/A
44665 AXI Bridge for PCI Express - No DRC for overrunning the AXI memory mapped space N/A N/A
44211 AXI Bridge for PCI Express - MSI interrupts only supports a single vector N/A N/A
44074 AXI Bridge for PCI Express - Enumerating multiple 64-bit BARs to 32-bit BARs might cause issues for Virtex-6 devices N/A N/A
43805 AXI Bridge for PCI Express - Mastering on the AXI-lite interconnect with a 64-bit AXI data width interface causes DECERR N/A N/A
43709 AXI Bridge for PCI Express - The GUI does not allow C_AXIBAR2PCIEBAR_# to accept 64-bit address values N/A N/A
43708 AXI Bridge for PCI Express - Changing C_AXIBAR_NUM does not grey out unused C_AXIBAR_# N/A N/A
43681 AXI Bridge for PCI Express - Root Complex Option does not have a DRC N/A N/A
43313 AXI Bridge for PCI Express - m_axi_arlock and m_axi_arcache are connected to the AXI write address channel N/A N/A
43263 AXI Bridge for PCI Express - AXI data width does not have a device dependent DRC N/A N/A
42642 AXI Bridge for PCI Express - AXI Interconnect frequency cannot be determined when using the axi_aclk_out clock N/A N/A
46563 AXI Bridge for PCI Express - Selecting 128-bit Interface Width for x8 Gen 1 or x4 Gen 2 results in ERROR:HDLCompiler:410 error N/A N/A
46100 AXI Bridge for PCI Express - x8 gen 1 for Virtex-6 FPGA should issue a DRC error N/A N/A
50633 AXI Bridge for PCI Express - Root Port Implementation does byte swap to the completion packet for a configuration read issued to an Endpoint device N/A N/A
50634 AXI Bridge for PCI Express - Memory Write to address 0x0000_0000 is treated as an MSI Request in Gen1X8 and Gen2X4 Endpoint configuration N/A N/A
51699 AXI Bridge for PCI Express - PCIe core not detected in Base System Builder (BSB) Design for KC705 Rev C Board N/A N/A
52677 AXI Bridge for PCI Express v1.04.a - The core runs into a Fatal Error during multiple MRds upstream N/A N/A
52678 AXI Bridge for PCI Express v1.04.a - Completion Payload greater than MPS Value N/A N/A
52679 AXI Bridge for PCI Express v1.04.a - Directed Link Change is not supported N/A N/A
52683 AXI Bridge for PCI Express v1.04.a - Latch and Sensitivity List Warning Messages N/A N/A
52684 AXI Bridge for PCI Express v1.04.a - Incorrect MSI Message routing in 128-bit mode operation N/A N/A
52685 AXI Bridge for PCI Express v1.04.a - Link trains down due to incoming MWr packets N/A N/A
52686 AXI Bridge for PCI Express v1.04.a - The core replies with incorrect data when reading Configuration Space for invalid Devices N/A N/A
52687 AXI Bridge for PCI Express v1.04.a - Default value of C_PCIEBAR2AXIBAR_*_SEC N/A N/A
52688 AXI Bridge for PCI Express v1.04.a - Completion TLP not generated when configured as Root Complex on Zynq devices N/A N/A
53511 AXI Bridge for PCI Express v1.05.a [Vivado 2012.3] - [IP_Flow 19_1710] Problem delivering 'Verilog Synthesis' files for IP 'axi_pcie_v1_05_a_0' N/A N/A
55348 AXI Bridge for PCI Express v1.07.a - Interrupt Decode Register gets wrongly set when performing DMA with ASPM enabled in RC mode N/A N/A
55349 AXI Bridge for PCI Express v1.06.a - AXI Bridge becomes unresponsive when performing DMA with ASPM enabled in RC mode N/A N/A
55350 AXI Bridge for PCI Express v1.06.a - The core in EP mode fails with corrupted data written to memory when configured for x4Gen2 on Zynq devices N/A N/A
55351 AXI Bridge for PCI Express v1.06.a - Missing completion for Memory Read when configured as RC x4Gen2 on Zynq devices N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46685 AXI Bridge for PCI Express - Support for Virtex-7 FPGA in 13.4 N/A N/A
46649 AXI Bridge for PCI Express - Spartan-6 32-bit inteface AXI Initiated Write Request Creates Malformed TLP N/A N/A
46647 AXI Bridge for PCI Express - zero-length write transactions on the AXI Slave port cause the AXI interface to hang N/A N/A
46646 AXI Bridge for PCI Express - In Root Port mode, memory read completion can be lost if Memory Read TLPs and Configuration TLPs are outstanding at the same time N/A N/A
46638 AXI Bridge for PCI Express - The bridge does not respond to memory read requests with a length of 0 when configured as x4 gen2 or x8 gen1 N/A N/A
46624 AXI Bridge for PCI Express - Using Root Port configuration a packet that does not actually target the BAR can be passed to the AXI Memory Mapped Bridge N/A N/A
46622 AXI Bridge for PCI Express - Large read request from AXI may cause completion timeout if link partner not releasing non-posted credits fast enough N/A N/A
46563 AXI Bridge for PCI Express - Selecting 128-bit Interface Width for x8 Gen 1 or x4 Gen 2 results in ERROR:HDLCompiler:410 error N/A N/A
46235 AXI Bridge for PCI Express - x8 gen1 and x4 gen2 do not have a DRC to ensure a 128-bit interface N/A N/A
45988 AXI Bridge for PCI Express - 1 DW Write Transactions on the AXI4 Slave interface create malformed TLPs when using a 32-bit AXI data width N/A N/A
45234 AXI Bridge for PCI Express - 64-bit TLPs are generated when requested address is less than 4GB N/A N/A
45078 AXI Bridge for PCI Express - Integer overflow error when simulating in NCSim N/A N/A
44976 AXI Bridge for PCI Express - Writes transactions to AXI4-lite Control Interface result in SLVERR N/A N/A
44211 AXI Bridge for PCI Express - MSI interrupts only supports a single vector N/A N/A
44074 AXI Bridge for PCI Express - Enumerating multiple 64-bit BARs to 32-bit BARs might cause issues for Virtex-6 devices N/A N/A
44665 AXI Bridge for PCI Express - No DRC for overrunning the AXI memory mapped space N/A N/A
44700 AXI Bridge for PCI Express - C_PCIEBAR2AXIBAR_# restriction on bits lower than C_PCIBAR_LEN_# N/A N/A
43709 AXI Bridge for PCI Express - The GUI does not allow C_AXIBAR2PCIEBAR_# to accept 64-bit address values N/A N/A
42642 AXI Bridge for PCI Express - AXI Interconnect frequency cannot be determined when using the axi_aclk_out clock N/A N/A
43681 AXI Bridge for PCI Express - Root Complex Option does not have a DRC N/A N/A
43708 AXI Bridge for PCI Express - Changing C_AXIBAR_NUM does not grey out unused C_AXIBAR_# N/A N/A
43313 AXI Bridge for PCI Express - m_axi_arlock and m_axi_arcache are connected to the AXI write address channel N/A N/A
43263 AXI Bridge for PCI Express - AXI data width does not have a device dependent DRC N/A N/A
43805 AXI Bridge for PCI Express - Mastering on the AXI-lite interconnect with a 64-bit AXI data width interface causes DECERR N/A N/A
46273 AXI Bridge for PCI Express - Kintex-7 simulation will not link train when C_PCIE_USE_MODE = 1.0 (IES) N/A N/A

Actions

AR# 44969
Date Created 11/22/2011
Last Updated 04/04/2013
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)
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