We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 44996

14.x Timing - Design Summary shows failing constraint but timing report shows 0 error


After completing implementation, I seeone failing constraint from the Design Summary window.

However, the timing report showszero errors and all my user constraints are replaced by a Default period and offset analysis.


You are seeing Default period and offset analysis because trce -a (Perform Advanced Analysis) is enabled. For more information, please refer to:
(Xilinx Answer 41316) - Design Summary shows failing constraints because the information is derived from PAR report (.par).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41316 14.x INFO:Timing:2700 - Timing constraints ignored N/A N/A
AR# 44996
Date Created 04/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less