**The fix for this issue is in the ISE 13.4 software, which is now available on www.xilinx.com/download**
The BUFPLL LOCK output in Bank 2 of all Spartan-6 devices does not function properly using ISE 13.3 and earlier software.
In ISE 13.4 and later software, the BUFPLL LOCK output behaves as expected in all banks. InISE 13.3 and earliersoftware, in all Spartan-6 devices, a modeling was identified for BUFPLLs in Bank 2 (BUFPLL_X1Y0, BUFPLL_X1Y1). As a result, the BUFPLL LOCK output has beenconnected High. Because the LOCK output is used only as a status signal, the BUFPLL and any IOLOGIC connected within Bank 2 will operate correctly. In the event that the PLL is reset, the BUFPLL output signals will be reset as well, consistent with normal BUFPLL operation, although LOCK will stay high throughout.
The BUFPLL LOCK output serves the exact same function as the PLL LOCKED signal except that it does not go high until the PLL has locked and the BUFPLL has aligned the SERDESSTROBE signal correctly. Because a user could be using the LOCK output to control the start of operation, designs may start before the BUFPLL or potentially the PLL has correctly locked. Designs using XAPP1064 in Bank 2 should be modified. MIG/MCB designs will not be affected.
The following show the LOCK behavior of the BUFPLL in Bank 2:
If ISE 13.4 cannot be used, some other options include: