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AR# 45028

Timing Analysis - How to meet timing for OFFSET IN?


What can I do to resolve OFFSET IN timing errors?


Unlike the Period constraint, the OFFSET constraints are more likely to be used for analysis or checking purposes.

There is not much the tool can do to adjust the design in order to meet the OFFSET constraints, especially when the input/output registers are placed into IOLOGIC's.

It is important that you select appropriate clock and data topologies for the interface to meet the OFFSET IN constraints or the timing requirements.

When OFFSET IN constraints are failing, please follow the below steps to find a solution.
1. Make sure the OFFSET IN constraints are correct.
2. Go to the Data sheet report section in the Timing report.

You can grab the following information from the "Offset Table" of the corresponding OFFSET IN Constraint in the Data sheet report.
  • If the (Setup Slack + Hold Slack) <0, it means it is impossible to meet both Setup and Hold requirements for the OFFSET IN constraint.
    If this is the case, you need to change the clock or data topology.
    See Steps 3.
  • If the (Setup Slack + Hold Slack) >=0, it means you have the opportunity to meet the OFFSET IN constraint by moving the clock edge to the middle of the data valid window by using the "Ideal Clock Offset To Actual Clock" value on top of the Table.
    See Steps 4.
Below is an example of the Offset Table in the Data sheet report:

3. The following are some clock and data topologies that are commonly used.
  • Place input registers into IOB's.
  • Add PLL/DCM/MMCM on clock path so that the clock insertion delay can be compensated and the clock edge can be phase shifted.
    Sometimes using PLL gives better results than DCM/MMCM because PLL reduces jitter and increases the margin.
  • Add IDELAY (fixed mode) on clock path so that the clock edge can be moved (delayed) by adjusting the IDELAY tap.
  • Add IDELAYs (fixed mode) on data paths so that the data window can be moved (delayed) relative to the clock edge by adjusting the IDELAY tap.
    This is also helpful when each data bit needs to be adjusted separately.
  • Add IDELAYs (fixed mode) on both clock and data paths.
    As the IDELAY component has a big variation between its min and max delay values, it usually eats into some of the margin when adding to only the clock path or data path.
    If IDELAYs are added to both the clock and data paths, the variation can be neutralized to save some margin.
  • Add PLL/DCM/MMCM on the clock path and IDELAYs (fixed mode) on data paths.
Each time you change the clock or data topology, you need to re-run Implementation and re-check the Data sheet report before adjusting the phase shift or the IDELAY tap value.

When the topology is changed, you will get a different scheme from the new implementation.
4. Determine how much you need to phase shift or delay to make the clock edge in the middle of the data window.

This is the value given by "Ideal Clock Offset To Actual Clock" on top of the Offset Table. In the above example, this value is -0.500ns.
  • A positive value means the clock edge needs to be moved forwards or the data moved backwards.
    A negative value means the clock edge needs to be moved backwards or the data moved forwards.
  • IDELAY can only move the clock or data forwards.
5. In some cases, the OFFSET IN constraint is not able to be met by any of the above topologies but the requirement on the interface is still under the best performance specified in the DC and Characteristics Data Sheet of the device.
The Static Timing Analysis gives the worst case analysis in fixed working mode.
The best performance that is declared in the DC and Characteristics Data Sheet can still be achieved by using IDELAY in variable mode for dynamic phase alignment.
In this scenario, OFFSET IN constraint analysis does not reflect the actual performance that can be achieved on the interface.
For instructions on dynamic phase alignment, please refer to the SelectIO Resources User Guide of the device.
Below are some application notes that you can refer to for dynamic phase alignment usage.
  • Spartan-6   XAPP1064
  • Virtex-6     XAPP1071
  • 7 series     XAPP585
AR# 45028
Date Created 11/15/2011
Last Updated 01/13/2015
Status Active
Type General Article
  • Vivado Design Suite