UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 45061

AXI Bridge for PCI Express - Instance names of the transceivers for location constraints

Description

This answer recordprovides instance names of important components in the AXI Bridge for PCI Express.

Solution

The following component names will be listed for Virtex-6 and Spartan-6 devices:

  • Clocking components: MMCM and PLL
  • PCI Express Integrated Blocks
  • Transceivers: GTX and GTP_DUAL

Virtex-6 FPGA

Clocking - MMCM_ADV
"*/pcie_clocking_i/mmcm_adv_i"

PCI Express Integrated Block - PCIE_2_0
"*/pcie_2_0_i/pcie_block_i"

Transceiver - GTXE1
"*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[0].GTX"
"*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/GTXD[1].GTX"

Spartan-6 FPGA

Clocking- PLL_BASE
"*_ep_inst/pll_base_i"

PCI Express Integrated Block- PCIE_A1
"*_ep_inst/PCIE_A1"

Transceiver- GTPA1_DUAL
"*/GT_i/tile0_gtpa1_dual_wrapper_i/gtpa1_dual_i"

Revision History
11/30/2011 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44972 AXI Bridge for PCI Express FAQ N/A N/A
AR# 45061
Date Created 11/30/2011
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • AXI PCI Express (PCIe)